Embedded memories are critical blocks in modern system-on-chip (SOC) integrated circuit. On many modern integrated circuits embedded memory arrays consume more than half of the die area. The penalty in terms of latency resulting from an off-chip memory access makes it desirable to include on-chip caches which are as large as possible. As CMOS technology scale deep into the nanometric regime the density of bitcells has significantly increased, resulting in much larger embedded memory for the same die area.
While embedded memories are important performance enablers, they come with many challenges. The difficulties in integrating large, dense embedded memories are primarily related to manufacturing. The scaling of CMOS has brought with it an increase in the process variability which designers must contend with. While variability used to be primarily systematic, as feature sizes scale below 100 nm random variability has become increasingly problematic. Systematic variability causes circuits to vary from die to die or wafer to wafer, while random variability can cause variations in the properties of adjacent transistors. There are numerous causes of random variability, including sub-wavelength lithography, random dopant fluctuations, line edge roughness and negative bias temperature instability (NBTI). Increasingly large embedded memories are being integrated into ICs, and as such the variability over the entire array can be very large. If sufficiently large design margins are not used in the design phase, variability can result in failures.
An SRAM array consists of a number of SRAM bitcells which are organized in multiple rows and columns in a plurality of blocks, as shown in FIG. 1. Each bitcell stores one bit of data; a logic value of zero or one. A bitcell usually has a control terminal wordline and a pair of data terminal called bitlines. During the read operation, the wordline becomes active and the cell draws a current from either one of the bitlines depending on the logic value stored in the cell. Voltage or current sense amplifiers are used to sense which one of the bitlines are affected by the cell current to detect the logic value that is stored in the cell. In order to save area, the sense amplifiers may be shared among a plurality of columns through multiplexer switches.
Sense amplifiers are important peripheral circuits in an SRAM array. Sense amplifiers are intrinsically amplifiers, and as such they operate by taking an input signal and amplifying it. In the case of a sense amplifier the goal is to take the differential signals which exist on the bitlines and output a full-swing signal which represents the state of the selected bitcell. If the amplifier has an intrinsic offset due to process variability then the size of the input signal will need to be large enough to compensate for that offset, or else an incorrect decision will be made. Transistor mismatch in the symmetric circuits that construct a sense amplifier play a key role in the creation of static offset for the sense amplifier.